Secure IoT Firmware For RISC-V Processors

March 26, 2021 Leave a comment


Credits: Embedded World Conference 2021 Proceedings, http://www.embedded-world.eu

Abstract — Building secure RISC-V devices is challenging as the RISC-V ISA doesn’t specify the hardware blocks necessary for the trusted execution of the many 3rd party components of the software stack. RISC-V developers are left alone figuring out how to shield trusted code from unverified 3rd party software libraries. In this paper, we introduce the industry-first secure IoT stack for RISC-V. We describe and explain all hardware and software components necessary to build state-of-the-art device, firmware, and cloud management service. These include RISC-V 32-bit SoC, MultiZone Trusted Execution Environment, TCP/IP connectivity, TLS/ECC cryptography, and MQTT client and broker providing telemetry and OTA applications deployment and firmware updates. All components are built on free and open standards, distributed under permissive licensing, and freely available for download from GitHub.

 

INTRODUCTION

Building secure IoT firmware for embedded devices is challenging. These resource-constrained devices typically lack the hardware resources necessary for the trusted execution of the many complex 3rd party software components required for secure operations. And state-of-the-art security features like secure boot, remote attestation, authenticated access to commercial cloud services, and over-the-air (OTA) firmware updates require a number of complex 3rd party software components [1,2]. Read more of this post

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A Clean Slate Approach to Linux Security RISC-V Enclaves

March 26, 2020 2 Comments


Credits: Embedded World Conference 2020 Proceedings, http://www.embedded-world.eu

Abstract – Hardware consolidation requirements and sophisticated new functional requirements are forcing embedded systems designers to mix safety-critical applications with complex rich operating systems. The resulting mixed-criticality systems present orders of magnitude larger code base and unacceptably greater attack surface and system vulnerability – often exposed to remote attack. To address this emerging threat model, we propose a new zero-trust computing architecture based on the concept of multi zone enclaves for RISC-V based Linux systems.

 

INTRODUCTION

We live in the era of the Internet-of-Things (IoT). Billions of interconnected devices are now integral part of our lives, perform a myriad of functions, manage safety-critical operations, and generate and process vast amounts of sensitive data. As these systems are connected to the external world, they are inherently exposed to an endless number of cybersecurity threads [1, 2]. As shown by many recent high-profile cybersecurity incidents, the viability of this new Internet era heavily depends on the security of these devices and on the trust we are willing to put on them [2]. Read more of this post

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RISC-V Open Source Processors Ready For Prime Time

March 4, 2019 Leave a comment

Excerpt of my interview with Elektronik
Harry Schubert, Chief Editor
February 2, 2019
https://www.elektroniknet.de/international/ready-for-series-production-162542.html

 

Based on the instruction set architecture RISC-V from the University of Berkeley, processor cores are now being developed as IP and SoCs. Cesare Garlati, founder Hex Five Security and chief security strategist at prpl Foundation, follows the development closely.

In the program of this year’s Embedded World Conference, RISC-V dominates the block »Hardware Engineering«. One of the speakers is Cesare Garlati, who accompanies the development of RISC-V and deals intensively with security aspects as a key member of the RISC-V Security Group and founder of Hex Five Security – the first Trusted Execution Environment for RISC-V. In an interview, he talks about the current state of technology.

Mr. Garlati How far has the development of a RISC-V ecosystem progressed?

The RISC-V ecosystem has grown tremendously from its beginnings as a research project at U.C. Berkeley.  As of Q4 2018 the Foundation has more than 220 members in 27 countries, many open source and commercial RISC-V cores are available and a robust ecosystem of peripherals, development and software tools.

Today you can find RISC-V solutions that cover everything from tiny 8-bit microcontrollers to 64-bit quad core running Linux. And even a more powerful 128-bit out-of-order core is in the makings at U.C. Berkeley – BOOM (Berkeley Out of Order Machine).

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A New Zero-Trust Model for Securing Embedded Systems

March 3, 2019 4 Comments

Credits: Embedded World Conference 2019 Proceedings, http://www.embedded-world.eu

Abstract — The attack surface in embedded systems has grown exponentially as connectivity requirements are increasingly met with the integration of readily available 3rd party libraries. A new Zero Trust Model is required to address the intrinsic security threat posed by the resulting monolithic firmware. This paper explores a new modern approach based on open source hardware and software where security through separation is achieved via a state-of-the-art multi-domain Trusted Execution Environment (TEE) for RISC-V processors.

INTRODUCTION
Embedded devices are a part of the daily lives of people all around the world. As devices get more personal and become placed in increasingly sensitive environments, the security of those devices becomes paramount. Security is a multi-tier approach, with different solutions being used across the industry depending on device capabilities and functionalities. Most security challenges faced by those resource-constrained devices that make up the Internet of Things can be minimized by enforcing physical separation between functional blocks and by properly implementing established encryption schemas to protect data in transit and at rest.

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Trusted Execution Environments – A System Design Perspective

March 3, 2019 Leave a comment

Credits: Embedded World Conference 2019 Proceedings, http://www.embedded-world.eu

Abstract — The Internet of Things (IoT) represents a collection of billions of smart, connected devices. Current approaches to securing IoT devices typically go through the addition of complex hardware mechanisms or the implementation of heavy containerization and virtualization solutions. In this paper, we take the reader through designing a real-world scenario of an IoT device making use of Trusted Execution Environments (TEE) to securely isolate different parts of the system. We aim to demonstrate a network connected device resembling a typical IoT device with a clear boundary separation between the application, the networking stack, and the root of trust.

INTRODUCTION
The Internet of Things (IoT) field has proliferated, with current estimates at 11 billion devices according to a recent Development Bank of Singapore (DBS) report [13]. According to the same report, privacy, security, and interoperability are the key barriers for widespread adoption [11]. While attempts at interoperability and standardization exist with organizations such as EdgeX [9], privacy and security still remain largely unaddressed. IoT devices do not work in isolation, they typically need to communicate with a central manager, posting their results and accepting commands from that central manager. Typical forms of communication involve protocols like BLE and TCP/IP. These protocols bring complex serializers and de-serializers often vulnerable to buffer overflow exploits, use after free and so on, with the latest examples being vulnerable TCP/IP stacks that could be exploited [12].

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User Mode Interrupts – A Must for Securing Embedded Systems

March 3, 2019 3 Comments

Credits: Embedded World Conference 2019 Proceedings, http://www.embedded-world.eu

Abstract — With the advent of the Internet of Things (IoT), devices are becoming smaller, smarter and increasingly connected. This explosion in connectivity creates a larger attack surface and new security threats. Recent cybersecurity attacks clearly demonstrated that the success of this new Internet era depends heavily on the security of those embedded devices that make up the IoT. In this paper, we argue in favor of a paradigm shift in the way computing systems are conceived and designed. We explain why the free and open RISC-V ISA promises to be a game-changer for embedded security, and we share our experience developing the industry-first RISC-V secure implementation of FreeRTOS based on MultiZone Security, the first Trusted Execution Environment for RISC-V. In the context of this research, we explain how to implement user-mode interrupts to secure modern embedded systems.

INTRODUCTION
The world is undergoing an unprecedented technological transformation, evolving from isolated systems to ubiquitous Internet-enabled ‘things’ capable of generating and handling vast amounts of security-critical and privacy-sensitive data [1]. This novel paradigm, commonly referred to as the Internet of Things (IoT), is a new reality that is enriching our everyday life but simultaneously creating several risks. Recent cybersecurity incidents, such as the Mirai Botnet, have clearly demonstrated that the success of this new Internet era is heavily dependent upon the trust and security built in these IoT devices.
The ongoing cat-and-mouse game of hacks and patches is largely due by the intrinsic lack of security of the traditional computing model, which is not safe nor secure. Mainstream operating systems (OSes) are designed for functionality and speed. These systems follow a monolithic architecture, with most of the services enjoying privileged execution rights. Typically, programs share the same access to code and data and functional blocks communicate via shared memory structures such as buffers, stacks and hypes – a single failure in one component can bring the entire system down [2]. Even more evolved systems that implements virtual memory protection schemas have shown several vulnerabilities, mainly due to the complexity of the software necessary to operate the underlying MMU [3].

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How to Secure a RISC-V Embedded System in Just 30 Minutes

March 1, 2019 Leave a comment

Credits: Embedded World Conference 2019 Proceedings, http://www.embedded-world.eu

Abstract — The free and open RISC-V ISA defines many important building blocks of security. Properly implementing them is the system designer responsibility. So, the real question is: How does one properly secure a RISC-V embedded system? This paper offers a practical guide to using these security blocks to build a state-of-the-art Trusted Execution Environment (TEE) with a multitude of isolated security domains – Zones, and secure communications between them. The paper also shows how to verify Zone isolation and benchmark overall TEE system performance.

INTRODUCTION
Originally developed at U.C. Berkeley, the free and open RISC-V ISA promises to bring the innovation and collaboration of the open source community to the hardware world. When it comes to security, RISC-V specifications [1] provide many important building blocks and the rapidly growing RISC-V ecosystem even more. For designers used to traditional closed-source proprietary architectures, the complexity associated with properly implementing these new security technologies may prove daunting [2].

From a system design perspective, the real question is: How do I properly secure a RISC-V embedded system? In this paper, we describe how to secure a RISC-V system using the free and open MultiZone Security Trusted Execution Environment (TEE) – developed and maintained by Hex Five Security, Inc. MultiZone Security provides signed boot, hardware enforced isolation for an unlimited number of security domains – Zones, a secure messaging system between Zones, secure interrupts, and operates on top of the standard RISC-V ISA.

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How to Build a RISC-V System In Just 30 Minutes

March 1, 2019 2 Comments

Credits: Embedded World Conference 2019 Proceedings, http://www.embedded-world.eu

Abstract — RISC-V is an open ISA (instruction set architecture) enabling a new era of innovation for processor architectures. RISC-V includes open source processor cores, toolchains, simulators and other key supporting components. The RISC-V ecosystem enables a new level of innovation in processor architecture that will be a key driver for the needed gains in performance and power efficiency over the next decade.

Introduction
The rapid growth of RISC-V has been truly impressive to witness. Originally developed at UC Berkeley as a means to support a graduate student project, the free and open ISA has become widely popular promising to bring the innovation and collaboration of the open source community to the hardware world – and to dramatically disrupt the whole semiconductor industry in the process.

So really the question is: How do I get started with RISC-V?

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RISC-V security: First piece of the puzzle falls into place

September 24, 2018 Leave a comment

 

By Thomas Claburn

10 Sep 2018 at 20:08

Credits: http://www.theregister.co.uk/2018/09/10/sifive_hex_five_riscv_secure_environment/

 

If you’ve been looking at SiFive‘s RISC-V-based chip technology and thinking, y’know what, it’s missing an Arm TrustZone-style element to run sensitive code, well, here’s some good news.

And if you’re just into processor design and checking out alternatives to Arm CPU cores, then this may be some interesting news.

SiFive helps organizations turn semiconductor designs based on the open-source RISC-V instruction set architecture (ISA) into chips. On Monday, it announced it has integrated Hex Five Security’s MultiZone Security trusted execution environment (TEE) into its Freedom SDK.

The technical confection gives companies creating RISC-V chips the tools to implement a security environment comparable to ARM’s TrustZone, though perhaps without past flaws. It should help users of the SiFive toolchain bring security-enforcing silicon to market faster.

Hex Five‘s technology, as its name suggests, allows for the creation of multiple isolated zones in which sensitive code – such as secure boot procedures and cryptographic routines – can run without interference from other programs or operating systems executing at the same time. It works with a Configurator tool that combines the compiled code with a Hex Five nanokernel to run within the secured environment.

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